1. Field of the Invention
The present invention relates to plasma display panels generally. More specifically, the present invention relates to an apparatus and method for controlling address power on a plasma display panel.
2. Description of the Related Art
A plasma display panel (PDP) includes a plurality of discharge cells arranged in a matrix format on a substrate. Images are displayed by selectively emitting various combinations of discharge cells. In this manner, video data input as electric signals is restored as an image that a user can see.
Color PDPs require shades of gray (gray scales) in order to present vibrant color pictures. Gray scales are provided by dividing the display into a plurality of subfields and controlling them in a time-varying manner.
For example, in the subfield method, each subfield is time-divided into a reset period for resetting a full screen, an address period for scanning the full screen in a line scanning manner and for programming data, as well as a sustain period for maintaining an emission state of the cells to which the data is programmed.
At least one address electrode is provided for performing an address operation. Similarly, at least one scan electrode is provided for performing a scan operation. Additionally, at least one common electrode is provided for performing a sustain operation. When the address electrode is driven in the PDP to display images, about 10 W to 500 W of power is consumed depending on resolution and size of the PDP. Conventionally, an address power recovery circuit is used to control the address power consumption. As described, power consumption of the displayed images with steeply increased address power consumption is controlled to some degree by using the address power recovery circuit. However, when an image without increased address power consumption is displayed, the address power recovery circuit continues to operate, and power consumption increases as a side effect.
The published Korean Patent Application No. 2002-32927 (A Method for Driving an Address Electrode of a Plasma Display Panel) discloses the side effect caused by a displayed image when the address power recovery circuit is operated. In this case, when a variation value of the input image data is less than a reference value, operation of the address power recovery circuit ceases. When the variation value exceeds the reference value, the address power recovery circuit operates to reduce the address power consumption. However in the above-noted application, only the variation value of the input image data is generated, and therefore, the address power recovery circuit stops operating for all subfields when the variation value is small, and operates when the variation value of the data is large. Accordingly, this and prior PDP systems control address power consumption ineffectively because the address data varies for each subfield, and the characteristics of the address power consumption differs for each subfield used to provide gray scales in a PDP.
Also, the higher the PDP's resolution and the wider its panel area become, the more the power is consumed when the address electrode is driven. Thus, it is difficult to control the power consumption using only the address power recovery circuit. A solution is needed that provides an improved apparatus and method for efficiently controlling address power consumption in a PDP.